MX66C256 rev. 1.1, jan., 2000 p/n ds0035 1 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com very low power 32k x 8 cmos sram pin configurations address input buffer row decoder memory array 512 x 512 column i/o write driver sense amp column decoder data buffer output address input buffer a3 a2 a1 a0 a10 data buffer input control gnd vdd oe we ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 a12 a11 a9 a8 a7 a6 a5 8 8 8 8 12 64 512 block diagram 512 18 a14 a13 a4 features vcc operation voltage : 5.0v very low power consumption : 50 ma (max.) write current 40 ma (max.) read current 0.4ua ( typ .) cmos standby current high speed access time : - 70 70ns (max.) - 100 100ns (max.) input levels are cmos-compatible automatic power down when chip is deselected three state outputs fully static operation data retention supply voltage as low as 2.0v easy expansion with ce and oe options the MX66C256 is a high performance, very low power cmos static random access memory organized as 32,768 words by 8 bits and operates at 5.0v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.4ua and maximum access time of 70ns and 100 ns in 5v operation. easy memory expansion is provided by an active low chip enable(ce), and active low output enable (oe) and three-state output drivers. the MX66C256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the MX66C256 is available in the jedec standard 28 pin 330mil plastic sop, and 8mmx13.4mm tsop (normal type). description a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 28-tsop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28-sop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 2 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com pin descriptions a 0 -a 14 address input these 15 address input select one of the 32768 x 8-bit words in the ram ce chip enable input ce is active low . chip enable must be active to read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. dq 0 - dq 7 data input/output ports these 8 bi -directional ports are used to read data from or write data into the ram. vcc power supply gnd ground mode we ce oe i/o operation vcc current not selected x h x high z i ccsb , i ccsb1 output disabled h l h high z i cc read h l l d out i cc write l l x d in i cc absolute maximum ratings (1) symbol parameter v term terminal voltage with respect to gnd rating units temperature under bias storage temperature power dissipation dc output current t bias t stg p t i out -0.5 to +7.0 -40 to +125 -60 to +150 1.0 20 v o c o c w ma operating range range ambien temperature industrial -40 o c to + 85 o c capacitance (1) (t a = 25 o c, f = 1.0 mhz) symbol parameter conditions max. unit c in c dq input/output capacitance input capacitance v in = 0v v i/o = 0v 6 8 pf pf 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not tested. truth table commercial 0 o c to + 70 o c vcc 4.5 ~ 5.5v 4.5 ~ 5.5v
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 3 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com dc electrical characteristics ( t a = 0 o to + 70 o c ) 1. typical characteristics are at t a = 25 o c. 2. these are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. f max = 1/ t rc . data retention characteristics ( t a = 0 o c to + 70 o c ) 1. v cc = 2.0v, t a = + 25 o c 2. t rc = read cycle time ce data retention mode v cc t cdr v cc t r v ih v ih vcc v dr 2.0v 3 ce vcc - 0.2v 3 low vcc data retention waveform (1) (ce controlled) parameter name guaranteed input low voltage (2) guaranteed input high voltage (2) input leakage current output leakage current parameter test conditions vcc = max, v in = 0v to vcc vcc = max, ce = v ih , or oe = v ih , v i/o = 0v to vcc vcc = 5.0v, i ol = 2ma vcc = 5.0v, i oh = -1ma ce=v il , i dq =0ma, f= fmax (3) output low voltage output high voltage operating power supply current min. max. -0.5 typ. (1) 0.3v cc 0.7v cc v cc+ 0.2 units v v ua 1 1 0.4 2.4 50 ua v v ma v il v ih i il i ol v ol v oh i cc symbol parameter test conditions vcc for data retention v dr min. max. typ. (1) units ce vcc - 0.2v, v in vcc - 0.2v or v in 0.2v ce vcc -0.2v, v in vcc - 0.2v or v in 0.2v data retention current chip deselect to data retention time operation recovery time see retention waveform 2.0 t rc (2) 0 0.20 v ua ns ns i ccdr t cdr t r 3 3 3 3 0.01 standby power supply current power down supply current ce = v ih , i dq = 0ma, ce vcc -0.2v, v in vcc - 0.2v or v in 0.2v 1 3 ma ua i ccsb i ccsb1 3 3 0.4 ce=v il , i dq =0ma, f=1mh z vcc = 5.0v vcc = 5.0v vcc = 5.0v vcc = 5.0v 40 ma
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 4 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com 70 70 50 35 30 ac electrical characteristics (over the operating range) read cycle switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh ac test conditions input pulse levels input rise and fall times input and output timing reference level 5.0/v0v 5ns 2.5v ac test loads and waveforms key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , w 667 thevenin equivalent all input pulses ? 10% ? 90% v cc gnd ? ? 5ns 90% 10% 1.73v output figure 2 5.0v output including jig and scope w 1923 w 1020 5pf figure 1b 5.0v output including jig and scope w 1923 w 1020 100pf figure 1a jedec parameter name parameter name description MX66C256-70 min. typ. max. unit read cycle time t avax t avqv t elqv t glqv t ehqz t ghqz t azqx t glqx t elqx t rc t aa t acs t oe t clz t olz t chz t ohz t oh address access time chip select access time chip select to output low z output enable to output in low z chip deselect to output in high z output disable to output in high z ns ns ns ns ns ns ns ns output enable to output valid ns 70 10 10 0 0 10 1. typical characteristics are at vcc = 5.0v, t a = 25 o c. output disable to output address change MX66C256-10 min. typ. max. 100 10 10 0 0 10 100 100 50 35 30
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 5 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com t oh read cycle3 (1,4) t rc t oe d out ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa read cycle2 (1,3,4) t clz t chz (5) d out ce (5) t acs notes: 1. we is high for read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low . 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested.
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 6 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com t wr ac electrical characteristics (over the operating range) write cycle jedec parameter name parameter name description MX66C256-70 min. typ. max. unit data hold from write time write cycle time t avax t e1lwh t avwl t wlwh t dvwh t ghqz t whqx t whdx t wlqz t whax t avwh t wc t cw t as t aw t wp t wr t whz t dw t dh t ohz t ow chip select to end of write address set up time address valid to end of write write recovery time write to output in high z data to write time overlap output disable to output in high z end of write to output active 30 30 ns ns ns ns ns ns ns ns ns ns ns switching waveforms (write cycle) write cycle1 (1) t wc (3) t cw (11) (2) t wp t aw t ohz (4,10) t as t dh t dw d in d out we ce oe address (ce , we) write pulse width (5) 70 70 0 70 50 0 40 0 0 5 1. typical characteristics are at vcc = 5.0v, t a = 25 o c.
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 7 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com write cycle2 (1,6) t wc t cw (11) (2) t wp t aw t whz (4,10) t as t dh t dw d in d out we ce address (5) t dh (7) (8) (8) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf as shown in figure 1b. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write.
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 8 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com ordering information speed ( ns ) ordering part number temperature range 70 100 70 100 70 100 70 100 0 o c to + 70 o c 0 o c to + 70 o c -40 o c to + 85 o c -40 o c to + 85 o c 0 o c to + 70 o c 0 o c to + 70 o c -40 o c to + 85 o c -40 o c to + 85 o c package type sop-28pin sop-28pin sop-28pin sop-28pin tsop-28pin tsop-28pin tsop-28pin tsop-28pin MX66C256mc- 70 MX66C256mc-10 MX66C256mi- 70 MX66C256mi-10 MX66C256tc- 70 MX66C256tc- 10 MX66C256ti- 70 MX66C256ti-10 n n package dimensions
MX66C256 rev. 1.1, jan., 2000 p/n ds0035 9 macronix america inc. usa 1338 ridder park dr., san jose, ca 95131 tel (408)453-8088 fax (408)451-0876 www. macronix .com n n package dimensions (continued)
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